The Race Beyond 2nm: New Materials and Architectures
The semiconductor industry is pushing beyond the 2-nanometer manufacturing node, entering a territory where traditional silicon transistor scaling faces fundamental physical limits. While TSMC, Samsung, and Intel have all announced mass production of 2nm-class chips in 2025 and 2026, the race is now on for the next generation of process technology that will define computing for the remainder of this decade. The stakes could not be higher: semiconductors are the bedrock of the modern economy, powering everything from smartphones and data centers to electric vehicles and military systems.
The transition from the 3nm to the 2nm node represented the first major architectural shift in decades, with all three leading foundries adopting the Gate-All-Around (GAA) field-effect transistor design. This architecture replaces the long-standing FinFET design by wrapping the gate completely around horizontal nanosheets or nanowires, providing better electrostatic control and reducing current leakage. TSMC’s N2 process (launched in late 2025) claims a 15% speed improvement or 30% power reduction over its N3P node, while Samsung’s SF2Z and Intel’s 18A offer similar competitive metrics.
But the real excitement — and uncertainty — lies beyond 2nm. The industry’s traditional path of simply shrinking transistors is reaching fundamental quantum-mechanical limits. At channel lengths below 10 nanometers, electrons can tunnel through insulating barriers, causing unacceptable leakage currents. This is driving exploration of entirely new transistor architectures, channel materials, and interconnection technologies that could define the next decade of semiconductor manufacturing.
Beyond Silicon: New Channel Materials
Silicon has dominated semiconductor manufacturing for over half a century, but at sub-2nm dimensions, its intrinsic material properties become limiting. Electrons move more slowly through ultrathin silicon channels, and the material’s relatively modest band gap contributes to leakage. Researchers at leading universities and corporate R&D labs are pursuing several promising alternatives.
Two-dimensional materials — particularly transition metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2) — have emerged as leading candidates. These materials can form atomically thin channels just one molecule thick, providing superior electrostatic control at nanometer-scale gate lengths. In 2025, researchers at MIT demonstrated a MoS2 transistor with a 0.5nm gate length — the smallest functional transistor ever created — though the device operated at cryogenic temperatures and practical mass production remains years away.
Germanium and III-V compound semiconductors (such as gallium arsenide, indium gallium arsenide, and gallium nitride) offer higher electron mobility than silicon, potentially enabling faster switching speeds at lower voltages. The challenge lies in integrating these materials onto silicon wafers without introducing defects at the interface. Intel has been pioneering hybrid bonding and wafer-scale heterogeneous integration techniques that could enable the practical combination of III-V materials with traditional silicon CMOS logic.
Carbon nanotubes (CNTs) have been a tantalizing alternative for two decades, but manufacturing challenges have prevented commercial deployment. The fundamental problem is placing billions of precisely aligned, chirality-controlled nanotubes at exact locations on a wafer. A breakthrough from MIT’s Max Shulaker group in 2025 demonstrated a CNT-based RISC-V processor with over 15,000 transistors fabricated using a novel “nanotube cleansing” process, representing the most complex CNT circuit ever built. While far from commercial, it demonstrates that CNT-based computing is physically possible.
New Transistor Architectures: CFETs and Beyond
Beyond GAA, the industry is preparing for the Complementary Field-Effect Transistor (CFET), which stacks NMOS and PMOS transistors vertically on top of each other rather than placing them side by side. This design can reduce standard cell area by up to 50% compared to GAA, enabling significantly higher transistor densities. IMEC, the Belgian nanoelectronics research center, has demonstrated working CFET structures at its R1 cleanroom facility in Leuven, projecting that the architecture will enter mass production at the A2 (Angstrom 2) node around 2028-2029.
Negative Capacitance FETs (NC-FETs) represent another promising avenue. By incorporating a ferroelectric material into the gate stack, NC-FETs can achieve sub-60mV/decade switching — breaking the so-called Boltzmann tyranny that has limited how steeply a transistor can transition between on and off states. Lower subthreshold swing means transistors can switch at lower voltages, dramatically reducing power consumption. While NC-FETs have been demonstrated in research settings, achieving reliable ferroelectric switching at nanoscale dimensions remains a formidable materials science challenge.
Tunnel FETs (TFETs) offer still another approach, using quantum tunneling rather than thermal emission to switch current on and off. TFETs can theoretically achieve sub-30mV/decade switching, offering even greater power efficiency. However, they typically suffer from very low on-currents — a problem researchers are addressing through new heterojunction materials and bandgap engineering at the source-channel interface.
Interconnects and Backside Power Delivery
As transistors continue to shrink, the wiring that connects them — the interconnect stack — becomes a growing bottleneck. At advanced nodes, signal delay in the copper interconnects can exceed transistor switching delay, limiting overall chip performance. The industry is pursuing several solutions, including the introduction of alternative metals such as ruthenium and molybdenum, which offer lower resistivity at nanoscale dimensions where copper’s resistivity increases dramatically due to electron scattering at grain boundaries and surfaces.
Backside power delivery has emerged as a critical innovation for sub-2nm chips. By moving the power delivery network from the front side (above the transistors) to the back side of the wafer, backside power delivery frees up routing resources on the front side, reduces voltage drop, and improves thermal management. Intel’s PowerVia technology, integrated into its 18A (1.8nm-class) process, has demonstrated significant performance and efficiency improvements. TSMC is expected to introduce its own backside power solution at the A16 node in 2027.
Optical interconnects — using light rather than electricity to transmit data between processor cores — represent a longer-term solution to the interconnect bottleneck. Silicon photonics has made significant progress, with Intel demonstrating integrated silicon photonic transceivers capable of 800 Gbps per channel. The full integration of optical interconnects into mainstream CMOS processes would revolutionize chip architecture, but significant manufacturing challenges remain, particularly in integrating efficient light sources (lasers) on a silicon platform.
The Economics of Next-Generation Manufacturing
The cost of building and operating leading-edge semiconductor fabs has reached staggering levels. A state-of-the-art 2nm-class fab now costs $20-30 billion, and the cost is expected to rise further for sub-2nm facilities. TSMC’s capital expenditure exceeded $36 billion in 2025, while Samsung and Intel have each committed over $20 billion annually to process development and capacity expansion. These enormous investments are reshaping the industry structure, with only three companies — TSMC, Samsung, and Intel — capable of manufacturing at the leading edge.
The economics of extreme ultraviolet (EUV) lithography are particularly challenging. ASML’s High-NA EUV systems, which began shipping to customers in 2024, cost approximately $400 million per machine. Each advanced fab requires 10-20 such machines, and the throughput — measured in wafers per hour — has been lower than initially projected. ASML has announced plans for a Hyper-NA EUV system for the A2 node and beyond, but the cost trajectory is causing concern even among the wealthiest chipmakers.
Government subsidies are playing an increasingly important role. The US CHIPS and Science Act has allocated $52.7 billion to domestic semiconductor manufacturing, while the European Chips Act provides €43 billion for European capacity. Japan, South Korea, India, and Germany have all launched substantial subsidy programs. These government investments reflect the strategic importance of semiconductor manufacturing, which is increasingly viewed through the lens of economic security and technological sovereignty rather than purely commercial factors.
Semiconductor supply chains are increasingly shaped by geopolitics. For more on how regulation is affecting technology, read our coverage on the EU AI Act and its global impact.
Geopolitics of Next-Generation Chips
Semiconductor technology has become central to great-power competition, particularly between the United States and China. US export controls, first imposed in October 2022 and progressively tightened through 2025, restrict Chinese access to advanced chip manufacturing equipment, particularly ASML’s EUV lithography systems. These controls have significantly slowed but not stopped China’s semiconductor advancement. Chinese companies are developing domestic alternatives, with SMIC reportedly producing 5nm-class chips using older DUV lithography equipment coupled with multi-patterning techniques.
The Netherlands, home to ASML, finds itself at the center of this geopolitical storm. The Dutch government has aligned with US-led export controls despite concerns about damage to ASML’s business model and Dutch economic interests. ASML’s CEO has warned that export restrictions could ultimately accelerate China’s drive for self-sufficiency, potentially creating a competing Chinese lithography industry within a decade. The company has also faced pressure to restrict service and maintenance contracts for existing installed systems in China.
Japan and South Korea are leveraging the current geopolitical environment to expand their semiconductor ecosystems. Japan’s Rapidus consortium, backed by government funding and partnered with IBM and IMEC, aims to manufacture 2nm-class chips by 2027. South Korea has announced a $472 billion investment plan centered on the “K-Semiconductor Beltway” in Yongin, creating the world’s largest semiconductor manufacturing cluster. The fragmentation of global supply chains, once seen as economically inefficient, is now viewed as a strategic imperative by governments worldwide.
The Road Ahead: 2027 and Beyond
The semiconductor industry’s roadmaps extend through the end of this decade and beyond, with the A2 (Angstrom 2, roughly equivalent to 0.6nm) and A1 (0.5nm) nodes targeted for 2028-2030. These nodes will likely require a combination of every innovation discussed above: CFET architectures, advanced channel materials including 2D TMDs, backside power delivery with novel interconnect metals, and High-NA/Hyper-NA EUV lithography. The integration of these technologies into a reliable, high-yield manufacturing process represents perhaps the most complex engineering challenge in human history.
Beyond the Angstrom era, the industry must confront fundamental questions about the future of computing. If transistor scaling can no longer deliver the performance and efficiency gains that have driven the industry for six decades, alternative approaches — including advanced packaging and 3D heterogeneous integration, specialized accelerators, neuromorphic computing, and ultimately fault-tolerant quantum computing — will become increasingly important. The semiconductor industry’s resilience and capacity for innovation suggest that reports of Moore’s Law’s death have been greatly exaggerated, but the path forward will look very different from the path behind us.
The next few years will determine which technologies, companies, and countries lead the post-silicon era of computing. The investments being made today — in R&D, fabrication capacity, and human capital — will shape the technological landscape for decades to come, determining everything from the capabilities of our smartphones to the trajectory of artificial intelligence and the balance of economic and military power among nations.
